Selective calling line controller for detecting and generating code characters



Sept. 29, 1970 s. A. DALYAI ETAL 3,531,772

SELECTIVE CALLING LINE CONTROLLER FOR DETECTING AND GENERATING CODECHARACTERS Filed Feb. 16, 1968 10 Sheets-Sheet 3 a: LL10: a: 2 3 0 IL) 0P 9, 1970 s. A. DALYAI ETAL 3,531,772

SELECTIVE CALLING LINE CONTROLLER FOR DETECTING AND GENERATING CODECHARACTERS Filed Feb. 16, 1968 10 Sheets-Sheet 4 m3 mm v ,2 JE mmw 8v A?E 03 Rm o A r U U c J63 Y m m x O2 TH P8 am A, mam 65 2w 748 o U mix JQS42H 37 m S 2N a i Q: 4 A law :00 u wrm mmm 3 5? 80 T I r Rm 2% 9 Eu 5m2% 65 8w v 5/ Sept. 29, 1970 s. A. DALYAl ETAL 3,531,772

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SQL 29, 1970 5, DALYA] ETAL 3,531,772

SELECTIVE CALLING LINE CONTROLLER FOR DETECTING AND GENERATING CODECHARACTERS Filed Feb. 16, 1968 10 Sheets-Sheet 6 Sept. 29, 1970 5 DALYAIETAL 3,531,772

SELECTIVE CALLING LINE CONTROLLER FOR DETECTING AND GENERATING CODECHARACTERS Filed Feb. 16, 1968 10 Sheets-Sheet 7 Sept. 29, 1970 s, D Y IETAL 3,531,772

SELECTIVE CALLING LINE CONTROLLER FOR DETECTING AND GENERATING CODECHARACTERS Filed Feb. 16, 1968 10 Sheets-Sheet 8 wmw vow :5 NR Us:

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SELECTIVE CALLING LINE CONTROLLER FOR DETECTING AND GENERATING CODECHARACTERS 1O SheetS -Sheet 10 Filed Feb. 16, 1968 5m Km omwm dodwm Gaomm vdq m United States Patent US. Cl. 340-163 12 Claims ABSTRACT OF THEDISCLOSURE A controller in a selective calling line selectively startsremote state transmitters and unblinds remote station receivers. Thecontroller provides a polling cycle for calling station transmitterswhich answer back by indicating the condition of the transmitter (i.e.,whether a message is available) and by starting the transmitter when itcontains a message. The controller stores the address signals in theheading of the message by marking individual stages of a shift register,which, in turn, controls a binary counter to retransmit thecorresponding address codes back over the multistation line sequentiallyand repeatedly until all addressee stations respond that they are readyto receive the message. If one or more addressee stations fail torespond, the heading with the code addresses of the stations failing torespond are sent to an intercept receiver. The addressee receivers arethen unblinded to record the message text. The controller also monitorsthe various answerback signals and the message heading and text. In theevent that the polled station fails to respond an improper answerback ormessage heading is received or a message text interruption occurs, atest poll cycle is initiated wherein the stations are polled todetermine conditions thereat without starting the message transmitter.Proper responses will now restore the polling cycle.

FIELD OF THE INVENTION This invention relates to binary code generationand registration and, more particularly, to apparatus in a multiplestation line controller for generating the outgoing binary codecharacters and registering the incoming codes.

DESCRIPTION OF THE PRIOR ART In data message distribution systems,groups of data stations are sometimes connected to a common transmission line to form a party or multistation line. In some party linesystems, messages are distributed on-line, i.e., the message originatesat one party line station and is destined for one or more of the otherparty line stations.

One example of a data distribution system having online deliveryinvolves a master station line controller which generates and transmitsbinary code characters to sequentially poll the party line stations todetermine whether the transmitters thereat have available messages. Thepolled station having a message thereupon proceeds to send the messageheading which contains appropriate call-in codes designating thedestination stations. These call-in codes are initially registered bythe line controller for subsequent retransmission to the party line toselect the designated recorders.

In on-line delivery systems, it is important to provide assurance thateach retransmitted call-in code is effective in selecting the addresseestation recorder. This assurance can be provided by arranging eachaddressee station to return an answerback response when the station 'icerecorder is selected by the call-in code. Accordingly, the linecontroller transmits each registered call-in code and pauses for theanswerback response before sending the call-in code to select the nextaddressee station. The line controller should be arranged to maintainthe registration of any call-in code when the answerback response is notreceived or when the response comprises a code signal which does notconfirm that the recorder is selected. The line controller can thenprovide another round of calls, sending only the call-in codes which hadnot received the answerback response indicating the selection of therecorder at the called station.

After call-in, the line controller restarts the sending station, wherebythe message text is recorded at the selected addressee stations. Whenthe message text transmission is terminated, the line controller resumesthe sequential polling for available messages, starting with the stationnext subsequent to the sending station.

There are many arrangements for generating and registering the binarycodes used for polling and calling in selected addressee stations.Advantageously, the sequential polling codes may correspond to binarynumbers. A binary counter can, therefore, be utilized as a generator ofthe codes since the counter output comprises sequential binary numbers.If the call-in code is identical to or corresponds to the polling code,the generation of these codes can also be provided by a binary counter.To generate a specific binary number, the corresponding numbered stageof a shift register can be marked (by inserting a signal bit therein,for example) and the marking shifted down and the counter concurrentlyadvanced until the marking is shifted to an initial stage. At this time,since the counter is counting the number of shifts, the counter outputcomprises the specific binary number. Thus, polling codes and call-incodes can be generated and transmitted by marking shift register stageswhose numbers correspond to the numbers of the stations to be polled orcalled in. This arrangement, however, does not provide for retainingregistrations, a feature necessary for call-in codes when the properanswerback response is not received. In addition, prior arrangements ofthis type do not disclose marking or more than one stage with provisionsfor pausing after each code generation for an answerback response.

It is an object of this invention to provide a binary code generatorcapable of generating binary code numbers and repeating the generationof selected ones of the binary codes. It is a further object that thegenerator pause after each generation until an answerback response isreceived.

It is obvious that the shift register functions to register the binarycodes when the shift register stages are marked. In order to mark theproper stage when a binary code is received, it has been suggested thatthe received binary code be temporarily stored in a multistage registerand a binary counter be advanced until the output matches the output ofthe multistage register. This identifies the binary number of thereceived code. If the initial stage of the shift register is marked andthe marking shifted up the shift register stages concurrently with eachadvance of the counter until the match is achieved with the receivedcode, the marking is advanced to the shift register stage number whichcorresponds to the binary number of the received code.

It is, of course, advantageous to provide a common shift register forgenerating and registering codes. Heretofore, however, this has not beenpossible because the contents of shift registers were shifted up thenumbered stages when codes are registered and down the numbered stageswhen codes are generated (assuming each stage is dedicated to acorresponding binary number). In addition, it can be seen that when asecond code is to be registered, the original marking, if not cleared,is shifted from its stage and its identity is lost.

Accordingly, it is another object of this invention to provide binarycode registration apparatus which includes a component, such as a shiftregister, that can also be included in generating apparatus. It is afurther object to register a plurality of code identities.

It is recalled that polling is resumed when message text transmission isterminated and, further, that the next subsequent station is the firstto be polled. Since a common shift register is preferred, it is seenthat the register must be remarked and reshifted, after handling thecall-in codes, back to the condition existing during the prior pollingstate. It is thus an object of this invention to restore the generatorto this condition.

SUMMARY OF THE INVENTION This invention contemplates new generating andregistering equipment for a multistation line controller. The generatingequipment includes a shift register for registering poll codes andcall-in codes, a binary counter for generating the poll codes, a binarycounter for generating the call-in codes and a clock for generating theshift pulses for the shift register and the advance pulses for thecounters. The clock, the shift register and the call-in binary counterare also utilized in the registering equipment.

In the illustrative embodiment of this invention, the line controller isprogrammed to operate through a plurality of different states undercontrol of a state logic circuit. In several of these states thegenerating and registering equipment is arranged to operate inaccordance with the objects of this invention. The prominent states ofinterest are the poll state wherein the poll codes are generated, theheading reception state wherein the call-in codes are registered, andthe heading delivery state wherein the call-in codes are generated andretransmitted.

It is a feature of this invention that, when codes are being generated,a marking can be recirculated to a final stage of the shift register.This feature is employed in the illustrative embodiment when the linecontroller is in the heading delivery state to enable the repeatedgeneration of call-in codes. It is also a feature of this invention thatthe marking is recirculated to the final stage when the answerbackresponse to the call-in code does not indicate that the addresseerecorder is selected or, alternatively, when no answerback response isreceived. Thus, in either event, the call-in code is again generated andtransmitted when the marking is recycled back to the initial stage. Itis another feature of this invention that the clock stops when a markingis advanced to the initial stage whereby the circuit pauses and awaitsthe answerback response. The clock restarts when the answerback responseis received.

It is a feature of this invention that, when codes are being registered,the initial stage is marked upon the match being achieved between thebinary counter and the input register. The marking can then berecirculated and shifted down the shift register stages until the binarycounter resets to the initial count. At this time the marking is shiftedto the stage number corresponding to the binary number of the code inthe input register since the number of stages after the marked stageequals the number of counts required to reset the binary counter afterthe match is achieved. Since marking is effected when the match isachieved and each operation requires the cycling of the counter, theshifting of the shift register is the same for generating andregistering and a different stage may be marked during each cyclingwithout overwriting or losing the identity of prior registrations. Thesefeatures are employed in the illustrative embodiment when the linecontroller is in the heading reception state.

In accordance with the illustrative embodiment, when the state logiccircuit terminates the poll state and initiates the heading receptionstate, further advance of the poll code binary counter is precluded. Atthis time, of course, the shift register registers the call-in codes inconjunction with the call-in binary counter. After the heading deliveryand the delivery of the text, the state logic circuit returns to thepoll state. It is a feature of this invention that the shift register isrestored to its prior condition in the poll state. With the shiftregister and the call-in counter in the initial position or count, theregister is cleared and the appropriate stages are marked to designatethe stations to be polled. The contents of the register are now shiftedand the call-in counter concurrently advanced until a match is obtainedbetween the call-in counter and the poll code counter. Since the pollcode counter advance has been precluded and the contents of the shiftregister have now shifted around to a condition corresponding to thepoll code counter advance, the prior poll state condition isreestablished. The poll code counter is now re-enabled and polling isresumed.

The foregoing and other objects and features of this invention Will befully understood from the following description of the illustrativeembodiment taken in con junction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The drawing comprises FIGS. 1 through11 wherein:

FIG. 1 discloses in block form the arrangement of the equipment of theline controller in accordance with this invention;

FIG. 2 shows a typical party line data station suitable for cooperationwith the line controller; and

FIGS. 3 through 10, when arranged as shown in FIG. 11, depict thecircuits of the state logic circuit which program the operations of theequipment of the line controller.

GENERAL DESCRIPTION The selective calling system of the presentinvention comprises a selective calling line controller shown in FIG. 1and a plurality of substantially identical party line stations, such asthe station shown in FIG. 2. These stations and the selective callingline controller are all interconnected by way of line 300. In general,each of the party line stations is arranged to communicate with one ormore of the other stations under the control of the station linecontroller of FIG. I. The controller provides supervision of thestations, testing each station to determine whether or not it isprepared to send messages and receive messages, selectively startingstations having message mate rial to send and cutting on addresseestations in accordance with the call-in codes in the heading of the datamessage.

The data in each message preferably comprises Arnerican Standard Codefor Information Interchange (ASCII) start-stop teletypewriter code,i.e., each data code character conventionally comprises an initial startsignal element, a final two element stop signal and intermediatecharacter elements utilizing the ASCII format. Each of the party linestations is specifically designated by a station polling code character(SPC) and a call-in code character (CEC). The SPC code and the CBC codecould be the same character for the station or, alternatively, could bedifferent characters. In any event, each character is an ASCII codecharacter. In this arrangement, the SPC character and the CEC characterare identical. Further, by inspection of the ASCII format it could beseen that each code character corresponds to a binary number.Accordingly, it may be said that each of the party line stationscorresponds to a binary number. This correspondence is specificallyutilized by the main station line controller, as disclosed hereinafter.

MAIN STATION LINE CONTROLLER Refer now to FIG. 1, showing the mainstation line controller. The controller is arranged to provide asequence of functions which is determined by the circuits in thecontroller and is further determined by responses of the several partyline stations to various code characters and character sequences appliedto line 300 by the main station line controller. The state logic,generally indicated by block 301, provides'the program for thecontroller which program defines the various steps and variousoperational sequences of the station line controller. The operation ofstate logic 301 is generally described here and the details of thecircuits of state logic 301 are described in a subsequent detaileddescription.

The line controller also includes a main shift register, generallyindicated by block 315. This shift register contains a plurality ofstages, including an initial stage for control purposes, a final stagefor entering certain bits and intermediate stages. Each of theintermediate stages corresponds to an individual one of the party linestations when main shift register 315 is in its initial state. With themain shift register in its initial condition, the first stage provides acontrol function, the next subsequent stage corresponds to the partyline station whose SPC and CEC codes correspond to the first binary number and each successive stage thereto corresponds to the party linestation designated by the subsequent binary number.

Main shift register 315 is arranged for serial and parallel inputting.One source of parallel inputting is provided by skip store 318 by way oftransfer gate 319. Skip store 318 includes a plurality of memoryelements. These memory elements are shown in FIG. 1 as mechanicalcontacts which extend a potential to a plurality of output leads. Thespecific type of memory elements in skip store 318 can, of course, beany other storage device so long as appropriate ones of the output leadshave potentials applied to them. The purpose of skip store 318 is toprovide an indication as to which of the outlying stations are to bepolled for message material and, conversely, which stations are to beskipped. Those stations which are to be polled are designated byenergizing their corresponding output leads, thus forming a skip table.Operation of the storage devices may be accomplished in any Well knownmanner.

Transfer gate 319 functions to pass the skip table to main shiftregister 315 when an activating pulse is sent to TRANSFER lead 263 bystate logic 301. Specifically, when TRANSFER lead 263 is pulsed, theskip table is passed from skip store 318 to main shift register 315 bytransfer gate 319, which inserts bits in each stage of register 315corresponding to each party line station to be polled for messagematerial.

State logic 301 also inserts bits (1 bits) in main shift register 315 byway of INSERT lead 299, INSERT II lead 349 and ENTER lead 340.Specifically, the pulsing of lead 299 inserts a bit in the first stageof register 315, the pulsing of lead 349 inserts a bit in the secondstage of register 315 and the pulsing of lead 340 may insert a bit inthe final stage of register 315. Conversely, the pulsing of DELETE lead264 removes any bit that might be stored in the first stage of mainshift register 315. (This is accomplished by inserting a bit in thefirst stage.) State logic 301 can also reset main shift register 315 bypulsing SET lead 250. The pulsing of lead 250 functions to insert a bitin the first stage and delete the bits in all the other stages of mainshift register 315. Finally, bits can be applied to the nth or lastintermediate stage of main shift register 315 by way of re-entry gate320. Specifically, state logic 301 may energize RIB-ENTER lead 332-,enabling re-entry gate 320 to recirculate bits from the first stage ofmain shift register 315 back through gate 320 to the nth stage of theregister.

The shifting of the bits in main shift register 315 is affected by shiftpulses derived from high speed clock 323. High speed clock 323 isarranged to develop clock pulses when enabled by clock control 322.Clock control 322, in turn, enables high speed clock 323 when either thefirst stage of main shift register 315 does not contain a bit or ENABLElead 267 is energized by state logic 301.

6 Thereafter, clock control 322 maintains high speed clock 323 enableduntil ENABLE lead 267 is deenergized and a bit is advanced to the firststage of register 315.

The output of high speed clock 323 is also passed to state logic 301 byway of high speed CLOCK lead 343, to the input of main binary counter314 and to the input of last poll store binary counter 316 by Way ofclock gate 324. It is noted that clock gate 324 is enabled to pass theclock pulses when an energizing signal is applied by state logic 301 toGATE lead 268.

Main binary counter 314 and last poll store binary counter 316 arearranged to provide a binary count, which count may be advanced to amaximum number equal to the number of stages in main shift register 315.Accordingly, each binary count corresponds to the number of each partyline station with the first binary number (0) corresponding to the onesupervisory stage in register 315.

Referring to main binary counter 314, when the count advances to thenumber of the last station plus one (n+1), n+1 detector 327 is operatedto pulse n+1 lead 408 which extends to state logic 301. In addition,detector 327 resets main binary counter 314. Thereupon, with counter 314reset to the initial count, all-0 detector 326 operates to pulse ALL 0lead 333. It is noted that last poll store binary counter 316 resets inthe same manner as main binary counter 314 although the correspondingn+1 detector is not shown.

The line controller is also provided with character shift register 308.Register 308 has a plurality of register stages corresponding to eachelement in the start-stop code characters. Code characters may beapplied in parallel to character shift register 308 by write gates 307.Specifically, state logic 301 may code individual characters on writegates 307 by way of CODE leads 254, (lead 254 com prising a cable for aplurality of coding leads). Alternatively, the binary number output oflast poll store counter 316 or main binary counter 314 is applied towrite gates 307 when state logic 301 energizes SPC lead 270 or CEC lead337, respectively. In any event, the particular code applied to writegates 307 is gated in parallel to register 308 when state logic 301pulses WRITE lead 255.

The parallel outputs of character shift register 308 are I applied tocharacter detection gates 312 and may also be applied to comparisoncircuit 317, as described hereinafter. Character detection gates 312,when enabled by start-stop clock 309, pulse DETECT leads 282 inaccordance with the character in register 308. DETECT leads 282 comprisea cable for a plurality of leads, each corresponding to a code characterof interest to state logic 301. Accordingly, in accordance with thecharacter in register 308, a particular one of DETECT leads 282 ispulsed and this pulse is passed to state logic 301. Serial inputting tocharacter shift register 308 is provided by data control 305. Incomingdata codes from line 300 are received by the receive portion of data set302. Data set 302 converts the line signals to the appropriatestart-stop code data signals which are passed to data control 305 and toidle line timer 403.

Consider for a moment idle line timer 403. This timer is arranged totime out when the incoming line is idle for a predetermined interval oftime, i.e., when no signals are received. Thereupon IDLE lead 392, whichextends to state logic 301, is pulsed.

Returning now to data control 305, when state logic 301 energizesINHIBIT lead 401, data control 305 blocks the passage of the datasignals from data set 302. Normally, however, data control 305 passesthe signals from the receive portion of data set 302 to the first stageof character shift register 308 and to start-stop clock 309. Thus, whena start signal is received, start-stop clock 309 starts up, appliesshift pulses to character shift register 308 to insert the charactertherein and, after the character is thus inserted, pulses characterdetection gates 312 to permit the gates to provide its detectionprocess. In addition, start-stop clock 309 may be started up by a pulseon START lead 251 from state logic 301. In this event, clock 309provides the usual shift pulses to character shift register 308 and, atthe termination of a start-stop cycle, pulses CLOCK lead 258. Finally,when start-stop clock 309 is started up, time out circuit 310 is pulsed.In the event that time out circuit 310 has been started by a pulseapplied to TIME OUT lead 272 by state logic 301, the pulse from clock309 resets time out circuit 310. In the event, however, that the timeout circuit 310 is not reset and thus times out, a pulse is applied tostate logic 301 by way of T/O lead 274.

Data control 305 is also arranged to pass serial output data fromcharacter shift register 308 to data set 302 or to typing unit 304.Specifically, in accordance with the manner that state logic 301energizes EXTEND leads 256, data control 305 may pass the datacharacters from register 308 to the send portion of data set 302 which,in turn, converts the characters to appropriate line signals forapplication to line 300. Data control 305 alternatively passes thesignal from output register 308 to typing unit 304, when EXTEND leads256 are energized in another manner, whereby the characters will beprinted to provide, as described hereinafter, various diagnosticprintouts.

As previously noted, the line controller also includes comparisoncircuit 317. This circuit is arranged by state logic 301 by way ofCOMPARE lead 265 to provide one of two alternate functions. The firstfunction is to compare the binary count output of counter 316 with theoutput of counter 314. The second function is to compare the output ofbinary counter 314 with the parallel output of character shift register308. In either event, when the comparison indicates that a match isattained, comparison circuit 317 pulses MATCH lead 266, which leadextends to state logic 301.

MAIN STATION LINE CONTROLLERGENERAL OPERATION The main station linecontroller is placed in its initial condition by the manual operation ofa key in state logic 301, which key is not shown in FIG. 1 but isdisclosed hereinafter with respect to the detailed description of statelogic 301. The operation of the initializing key operates state logic301 to place the circuit in the initializing state. In this state, statelogic 301 operates to pulse SET lead 250, whereby a bit is entered inthe first stage of main shift register 315. Concurrently, RESET lead 253is pulsed to reset main binary counter 314. Accordingly, main shiftregister 315 is placed in its initial condition and main binary counter314 is reset to its initial count.

At this time state logic 301 enables CODE leads 254 to code the enquirycharacter ENQ on write gates 307. WRITE lead 255 is also pulsed, passingthe code ENQ to character shift register 308. In addition, EXTEND leads256 are energized in a manner to enable data control 305 to extend theserial output of shift register 308 to data set 302. Finally, in theinitializing state, state logic 301 pulses START lead 251, thusactivating the operation of start-stop clock 309 which, in turn, appliesshift pulses to register 308. Accordingly, the code character ENQ isshifted out of shift register 308, passed by way of data control 305 tothe send portion of data set 302 and thus converted to line signals forapplication to line 300.

At the termination of the transmission of code character ENQ, theoperation of start-stop clock 309 terminates, whereby CLOCK lead 258 ispulsed. State logic 301 in response thereto codes theend-of-transmission character EOT on write gates 307 by way of CODEleads 254. WRITE lead 255 is also pulsed to enable write gates 307 topass the code character to register 308. In addition, state logic 301enables data control 305 to again extend the output of shift register308 to data set 302. Finally, START lead 251 is again pulsed, start-stopclock 309 again initiates its operation and the code character EOT isthus passed on to line 300. Accordingly, the code sequence ENQ- EOT istransmitted to the party line stations. As described hereinafter, thiscode sequence has the effect of clearing the party line stations, whichare then prepared to be test polled.

After the code character EOT is transmitted, startstop clock 309 pulsesCLOCK lead 258, stepping state logic 301 to the initializing test pollstate. In this state, state logic 301 steps start-stop clock 309 throughtwo cycles. All of the other functions are suppressed, however, in thisstate, for reasons more fully set forth in the detailed description ofthe state logic circuit.

At the end of the second cycle of start-stop clock 309 a pulse is againreturned on CLOCK lead 258. At this time state logic 301 pulses TRANSFERlead 263. This enables transfer gate 319 to pass the skip table in skipstore 318 to main shift register 315. State logic 301 now enablescomparison circuit 317 by way of COMPARE leads 265 to compare theoutputs of main binary counter 314 with the output of last poll storebinary counter 316. If comparison circuit 317 indicates by way of MATCHlead 266 that the outputs are not identical, state logic 301 energizesENABLE lead 267. Accordingly, high speed clock 323 is enabled toconcurrently advance main shift register 315 and main binary counter314. This advance continues until a comparison is reached betweencounters 314 and 316, at which time comparison circuit 317 returns amatch signal on lead 266 to state logic 301. Thus, counter 314 andregister 315 are advanced to coincide with the position of counter 316.It is noted, however, that in the initialized state, counter 316 can beconsidered to be normally at the initial position. Thus, main binarycounter 314 is matched with counter 316 and state logic 301 does notenergize ENABLE lead 267 since a match is initially obtained.

Upon the attaining of the match, state logic 301 energizes GATE lead 268to connect the output of high speed clock 323 to last poll store binarycounter 316. At the same time, DELETE lead 264 is pulsed, removing thebit in the first stage of register 315, enabling clock control 322 tomaintain high speed clock 323 operating. Thus, counters 314 and 316,which are now matched with each other and with register 315, areconcurrently advanced with register 315 until the next bit advances tothe first stage of main shift register 315. This bit corresponds to thebit from the skip table, which designates a station to be polled. (Thisis the first station on the skip table when state logic 301 is in theinitialized test poll state wherein the counters are in the initialposition.) The appearance of the bit in the first stage stops clock 323by way of clock control 322. Accordingly, main binary counter 314 andlast poll store binary counter 316 are advanced to a count correspondingto the binary number of the outlying station to be polled.

In the initializing test poll state, state logic 301 also codes thecharacter DLE on write gates 307 and pulses WRITE lead 255 to pass thecode character DLE to shift register 308. Data control 305 is alsoenabled to extend the output of register 308 to data set 302. Finally,state logic 301 starts up start-stop clock 309, whereby the codecharacter DL-E is passed to line 300.

After the transmission of code character DLE, startstop clock 309 pulsesstate logic 301. In the initializing test pole state, state logic 301energizes SPC lead 270, whereupon the station poll character or binarynumber of the first station to be polled is coded on write gates 307 bylast poll store binary counter 316. State logic 301 also pulses WRITElead 255 to pass the station poll character to shift register 308. Datacontrol 305 is also enabled to extend the output of shift register 308to data set 302 and start-stop clock 309' is enabled, whereby thestation poll code is transmitted to line 300. At this time state logic301 pulses TIME out lead 272, enabling time out circuit 310 to start itstime out operation.

Summarizing the above sequence of operations, it is seen that after thecode sequence ENQ-EOT is sent to the line during the initializing state,state logic 301 enables the controller circuit to advance counters 314and 316 together with register 315 to the position corresponding to thefirst station to be polled and arranges the generation of the codesequence DLE-SPC, (the code character SPC corresponding to the stationpoll code of the first outlying station). As described hereinafter, theoutlying stations view the code character DLE following the codesequence ENQ-EOT as the start of the test poll. Each station thenresponds to its own station poll code. The response will be the codecharacter ACK if a message is available, the code character NAK if nomessage is available, or the code character CAN if a previous messagewas improperly received.

Assume now that the polled outlying station does not respond to thestation poll code. In this event, after a predetermined interval oftime, time out circuit 310 operates to pulse T lead 274. In responsethereto state logic 301 codes write gates 307 with the character T,enables write gates 307 to pass the code character to shift register308, enables data control 305 to extend the serial output of shiftregister 308 to typing unit 304 and starts start-stop clock 309. Thus,the code character is printed by typing unit 304.

At the termination of this printing, start-stop clock 309 pulses CLOCKlead 258. Thereupon, state logic 301 codes Write gates 307 with thestation poll code from last poll store binary counter 316. Write gates307 are also enabled to pass the code character to shift register 308and data control 305 extends the output of shift register 308 to typingunit 304. Finally, start-stop clock 309 is operated by way of START lead251. Thus, the station poll code is printed by typing unit 304.Accordingly, a diagnostic printout is made indicating that a time outhas occurred and identifying the outlying station which has notresponded to the polling.

At the termination of the diagnostic printout start-stop clock 309pulses CLOCK lead 258. State logic 301 then deletes the bit in the firststage of main shift register 315. This enables high speed clock 323 toadvance counters 314 and 316 together with register 315 until the nextbit in the skip table advances to the first stage of main shift register315. High speed clock 323 thereupon stops and the station poll code ofthe next outlying station is generated and transmitted to line 300 inthe same manner as previously described.

Summarizing the operations that occur when the outlying station fails torespond, time out circuit 310 times out, pulsing state logic 301. In theinitializing test poll state, state logic 301 arranges a diagnosticprintout indicating that time out has occurred, together with a printingof the station poll code. After the printout, counters 314 and 316,together with register 315, are advanced to the position correspondingto the next station to be polled and its poll code is thereupongenerated and transmitted to line 300.

Assume now that the polled outlying station responds with a garbled ornon-designated character (i.e., a code character not ACK, NAK or CAN).In this event the code character is received from line 300 by data set302 and passed by way of data control 305 to character register 308. Atthe same time the start pulse of the character enables start-stop clock309 to shift the code elements into register 308 and, at the same time,to reset time out circuit 310.

When the garbled or nondesignated character is fully received,start-stop clock 309 pulses character detection gates 312, enabling thegates to pass by way of DETECT lead 282 an indication that anondesignated character has been received. In response thereto statelogic 301 codes write gates 307 with the bad response character R,enables write gates 307 to pass the character to shift register 308,enables data control 305 to extend the output of register 308 to typingunit 304 and starts start-stop clock 309. Thus, the code character R isprinted by typing unit 304.

At the termination of this printing, start-stop clock 309 pulses CLOCKlead 258. Thereupon, state logic 301 energizes SPC lead 270, thus codingwrite gates 307 with the station poll code from last poll store binarycounter 316. Write gates 307 are also enabled, as is data control 305,to permit typing unit 304 to print the station poll code in the samemanner as previously described with respect to the time out printout.Accordingly, a diagnostic printout is made, indicating that a garbled ornondesignated character has been received and identifying the outlyingstation which has made this nondesignated response.

At the termination of the diagnostic printout, start-stop clock 309pulses CLOCK lead 258. State logic 301 then proceeds to delete the bitin the first stage of main shift register 315. This enables high speedclock 323 to advance counters 314 and 316 together with register 315 tothe next station to be polled, whereby the station poll code of the nextoutlying station is generated and transmitted to line 300 in the samemanner as previously described.

Summarizing the operations that occur when the outlying station returnsa garbled or nondesignated character, detection gates 312 indicate tostate logic 301 the nondesignated response. State logic 301 thereuponarranges a diagnostic printout indicating that a nondesignated responsehas been received, together with a printing of the station poll code.After the printout, counters 314 and 316, together with register 315,are advanced to the position corresponding to the next station to bepolled and its poll code is thereupon generated and transmitted to line300.

Assuming now that the polled outlying station responds with the cancelcharacter CAN. Upon the reception of the character by data set 302,start-stop clock 309 is operated to reset time out circuit 310 and shiftthe character into shift register 308, as previously described.Detection gates 312 then indicate to state logic 301 that the codecharacter CAN has been received. In response thereto, state logic 301codes Write gates 307 with the character C, energizes write gates 307together with data control 305, and starts start-stop clock 308. Thus,the character C is printed by typing unit 304 in the same manner aspreviously described.

At the termination of this printing, start-stop clock 309 pulses CLOCKlead 258. Thereupon, state logic 301 en ergizes SPC lead 270, thuscoding Write gates 307 With the station poll code from last pollstorebinary counter 316. State logic 301 also pulses write gates 307 topass the code character to shift register 308, data Control 305 isenergized and start-stop clock 309 is operated to permit the printing ofthe station poll code by typing unit 304. Accordingly, a diagnosticprintout is made, indicating that the polled station has responded thatthe previous message was improperly received and identifying theoutlying station which has so responded.

At the termination of the diagnostic printout startstop clock 309 pulsesCLOCK lead 258. State logic 301 thereupon deletes the bit in the firststage of main shift register 315 to advance counters 314 and 316,together with main shift register 315, to the next station to be polled.At this time state logic 301 advances to the poll state.

Summarizing the operations that occur, when the outlying stationresponds with the code character CAN, the code character is received byshift register 308 and character detection gates 312 pulse state logic301 to indicate the reception of this particular character. State logic301, in turn, arranges a diagnostic printout indicating that theoutlying station has responded that the previous message was receivedimproperly together with a printing of the station poll code. After theprintout counters 314 and 316, together with register 315, are advancedto the position corresponding to the next station to be polled. Statelogic 301 at that time steps to the poll state.

Assuming now that the outlying station in response to the test pollreturns the code character NAK to indicate that the station has nomessage available. Upon the reception of the code character, start-stopclock 309 resets time out circuit 310 and shifts the code character intoregister 308. Character detection gates 312 thereupon pulse state logic301 to indicate that the outlying station has returned a designatedresponse but does not have message material to transmit. Thereupon,state logic 301 deletes the bit in the first stage of main shiftregister 315 to advance counters 314 and 316, together with register315, to the next station to be polled. State logic 301 thereupon stepsto the poll state.

If the outlying station responds to the test poll with the codecharacter ACK, indicating that a message is available, time out circuit310 is reset, as previously described, and the character is shifted intoregister 308 by startstop clock 309. Character detection gates 312thereupon indicate to state logic 301 that a station has responded thata message is available. State logic 301, in response thereto, steps tothe poll state. It is noted that state logic 301 does not advancecounters 314 and 316. Accordingly, the counters are maintained on theposition corresponding to the station responding to the test poll withthe character ACK.

When state logic 301 steps to the poll state, CODE leads 254 areenergized in a manner to code the character DLE on write gates 307.State logic 301 also enables write gates 307 to pass the character toshift register 308, enable start-stop clock 309 to produce shift pulses,whereby shift register 308 serially shifts out the code character, and,finally, energizes EXTEND leads 256 in a manner to enable data control305 to extend the output of shift register 308 to data set 302.Accordingly, the code character DLE is passed to line 300.

At the termination of the transmission of the character DLE, start-stopclock 309 pulses state logic 301 by way of CLOCK lead 258. State logic301, in turn, pulses SPC lead 270, whereby the binary output code fromlast poll store binary counter 316 is applied to Write gates 307. Statelogic 301 again pulses WRITE lead 255 and START lead 251, whereby thestation poll character is passed to shift register 308 and seriallyshifted out to data control 305. In addition, state logic 301 againenables data control 305 to extend to the output of shift register 308to data set 302, thus passing the station poll code to line 300.Finally, state logic 301 pulses TIME OUT lead 272, thereby initiatingthe operation of time out circuit 310.

Summarizing the above sequence of operations, it'is seen that when statelogic 301 steps to the poll state it arranges the generation of the codesequence DLE- SPC. As described hereinafter, the outlying stations viewthe code character DLE when not following the code sequence ENQ-EOT asthe start of a normal poll and not as a test poll. Each station thenresponds to its own station poll code. This response will be the codecharacter CAN if the previous message was improperly received, the codecharacter NAK if no message is available and the start-of-headingcharacter SOH, which may or may not be preceded by Delete characters, ifa message is available. The reception of the start-ofheading characterSOH or the Delete character indicates the station is proceeding to sendthe heading of the message.

Assume now tht the polled station fails to respond to the station pollcode. In this event, after a predetermined interval of time, time outcircuit 310 operates to pulse T lead 274. In response thereto statelogic 301 goes to the major alarm state. In this condition. state logic301 functions in substantially the same manner as in the initializingstate, wherein, as previously described, main binary counter 314 isreset and main shift register 315 is cleared with a bit entered in thefirst stage. In addition, the code sequence ENQ-EOT is generated andtransmitted to line 300. It is noted at this time that last poll storebinary counter 316 remains at the position 12 corresponding to thestation which has failed to respond. The code sequence ENQEOT clears theparty line stations, placing them in a condition to respond to a testpoll.

Returning now to the line controller, start-stop clock 309 pulses statelogic 301 when the transmission of the code sequence ENQ-EOT isconcluded. State logic 301 in response thereto advanced to the test pollstate. In this condition state logic 301 operates in a manner similar tothe initializing test poll state, wherein a diagnostic printout isprovided, which, in this case, is the code sequence T-SPC. (The SPCcorresponds to the station which fails to respond since counter 316 hasbeen maintained on the corresponding position.) After the printout theskip table is again entered in main shift register 315 and counter 314is stepped with main shift register 315 until a match is obtainedbetween counters 314 and 316. The bit is deleted from the first stage ofmain shift register 315 at this time whereupon counters 314 and 316,together with main shift register 315, are stepped to the next stationto be polled and the code sequence DLE-SPC is transmitted. State logic301 thereafter remains in the test poll state until a proper response isreturned by a polled station. Thus, as previously described with respectto the initializing test poll state, each station is polled, diagnosticprintouts are provided if the proper response is not received, and, if aproper response is received, state logic 301 advances again to the pollstate.

Return now to the advancing of state logic 301 to the poll state and thepolling of the outlying station. Assume that the polled station respondswith a garbled character, i.e., that the response does not comprise anyone of the characters SOH, NAK, CAN or Delete. When the start element ofthe non-designated character is received by data set 302 and passed toregister 308, start-stop clock 309 is enabled, resetting time outcircuit 31.0 and shifting the character into register 308. At thetermination of the reception of the character, detection gates 312 pulsestate logic 301 to indicate that a non-designated character has bbeenreceived. In response thereto, state logic 301 goes to the major alarmstate. In this condition, as previously described, state logic 301resets binary counter 314, clears main shift register 315 and generatesthe code sequence ENQ-EOT for transmission to line 300. The party linestations are thus cleared, placing them in condition to respond to thetest poll. Thereafter, state logic 301 advances to the test poll stateand provides a diagnostic printout of the code sequence R-SPC whereinthe code character SPC corresponds to the station which had respondedwith the garbled character. After the printout the skip table is againregistered in main shift register 315, a match is obtained betweencounters 314 and 316 and the counters, with shift register 315, arestepped to the next station to be polled in the same manner aspreviously de scribed. The code sequence DLE-SPC is then transmitted totest poll the next station and the previously described test pollprogram is again provided.

Returning again to the poll state wherein the line con troller polls theoutlying station, assume now that the polled station responds with thecode character CAN. In this event, start-stop clock 309 resets time outcircuit 310 and shifts the code character into shift register 308. Afterthe character is received, detection gates 312 pulse state logic 301.State logic 301, in response to the detec tion of the code characterCAN, codes write gates 307 with the printout code character C, pulsesthe write gates to pass the character to shift register 308, enablesstart-stop clock 309 and energizes EXTEND leads 256 in a manner toenable data control 305 to extend the output of shift register 308 totyping unit 304. Thus, the character C is printed by typing unit 304.

After the printing of the character C, start-stop clock 309 pulses statelogic 301. State logic 301, in turn, pulses SPC lead 270, enabling lastpoll store binary counter 316 to code write gates 307 with the stationpoll code of the 13 outlying station which responded with the codecharacter CAN. State logic 301 also pulses WRITE leads 255, EXTEND leads256 and START lead 251, whereby the station poll code is passed throughwrite gates 307 to shift register 308 and then to typing unit 304. Thus,a diagnostic printout is provided, indicating that the polled stationhas responded that the previous message was improperly received.

After the printout of the code sequence C-SPC, state logic 301 deletesthe first bit in main shift register 315. This enables high speed clock323 to concurrently advance counters 314 and 316, together with mainshift register 315, until the next station to be polled is reached. Atthis time state logic 301 pulses SPC lead 270, coding the station pollcode of this next station on write gates 307. State logic 301 alsoenables write gates 307 to pass the station poll character to register308 and then, by way of data control 305, to data set 302. Accordingly,the station poll code is transmitted to line 300. Since the outlyingstations are presently looking for poll codes, the polled stationresponds to its code in the same manner as previously described.

Assume now that, with state logic 301 in the poll state, a stationresponds with the character NAK, indicating that no message is availablethereat. Upon the reception of the character, start-stop 309 resets timeout circuit 310 and shifts the character into register 308. After thecharacter is received, detection gates 312 pulse state logic 301. Inresponse thereto state logic 301 deletes the bit in the first stage ofmain shift register 315, whereby high speed clock 323 advances counters314 and 316, together with register 315, to the next station to bepolled. State logic 301 thereupon pulses SPC lead 270, whereby, aspreviously described, the station poll code of the next station isgenerated and passed to line 300. At the same time TIME OUT lead 272 ispulsed to reinitiate the operation of time out circuit 310. Accordingly,the next station poll code is transmitted and the line controlled awaitsthe response, in the same manner as previously described.

If the polled outlying station has a message available it responds tothe poll code by sending the message heading. The start-of-messagecharacter SOH designates the first character of the message heading.This character, however, may be preceded by Delete or fill characters inthe message tape.

Assume first that a Delete character is received from the polledstation. Upon the reception of the character, start-stop clock 309resets time out circuit 310 and shifts the character into register 308.Detection gates 312 thereupon pulse state logic 301 and the logiccircuit advances to the wait-for-heading state. In this state, TIME OUTlead 272 is pulsed to enable time out circuit 310 to again operate. Foreach subsequent Delete character start-stop clock 309 again resets timeout circuit 310 and state logic 301 thereafter restarts time out circuit310. In this manner the several Delete characters are received and thestate logic awaits the startof-heading character SOH.

If during the wait-for-heading state the outlying station ceases totransmit, time out circuit 310 times out and pulses state logic 301.This advances state logic 301 back to the poll state. Upon advancing tothe poll state, state logic 301 deletes the bit in the first stage ofmain shift register 315 to advance counters 314 and 316, together withregister 315, to the position corresponding to the next station to bepolled. Thereupon, state logic 301 arranges the generation of codecharacter sequence DLE-SPC (character SPC comprising the station pollcharacter of the next station). Accordingly, station polling is resumedand the station poll character of the next station to be polled istransmitted to line 300.

Return now to the line controller in the wait-forheading state. If theoutlying station responds with a garbled or nondesignated character,i.e., with a character other than Delete or SOH, start-stop clock 309 isenabled, as previously described, to reset time out circuit 310 andshift the garbled character into register 308. Detection gates 312 thenpulse state logic 301, indicating that a garbled character has beenreceived. State logic 301 thereupon advances to the major alarm state.

In the major alarm state, as previously described, state logic 301resets main binary counter 314, clears main shift register 315 andgenerates and transmits the code sequence ENQ-EOT to clear the partyline stations. After this major alarm code sequence is generated statelogic 301 advances to the test poll state wherein a diagnostic printoutis provided. In this case the printout includes the bad headingcharacter H followed by the station poll code of the party line stationwhich responded with the nondesignated character.

At this time counter 314 and register 315 advance until a match isachieved with counter 316. The bit is deleted in the first stage of mainshift register 315 and the circuits again advance to the next station tobe polled. The code sequence DLE-SPC is now generated and transmitted,as previously described, whereby the test poll of the next station isprovided. Test polling will then continue until a proper response isreceived.

It is recalled that while state logic 301 is in the poll state or in thewait-for-heading state, the outlying station may return thestart-of-heading character SOH. In either event the reception of thecharacter SOH operates start-stop clock 309 to reset time out circuit310 and shift the character into register 308. Detection gates 312 thenpulse state logic 301 to indicate that the start-of-heading characterhas been received. State logic 301, in turn, advances to the headingreception state.

In the heading reception state, state logic 301 energizes COMPARE leads265 in a manner to arrange comparison circuit 317 to compare the outputof main binary counter 314 with the output of character shift register308. In addition, state logic 301 clears main shift register 315,writing a bit in the first stage of the register and clearing the otherstages. State logic 301 also resets main binary counter 314 and restartstime out circuit 310. In addition, state logic 301 energizes RE-ENTERlead 322, whereby re-entrant gate 320 is enabled to recirculate bitsfrom the first stage of the main shift register 315 in the nth stage. Inthis heading reception state the line controller is prepared to receivethe message heading from the sending station and register the addresscodes in the message heading.

When an address character is received, time out circuit 310 is reset andthe call-in or address code is entered in character shift register 308.At the conclusion of the reception of the address code, start-stop clock309 pulses state logic 301. Thereupon, state logic 301 restarts time outcircuit 310 and energizes ENABLE lead 267. This starts up high speedclock 323, concurrently advancing main binary counter 314 and main shiftregister 315. When main binary counter 314 advances to a countcorresponding to the binary number individual to the call-in code, amatch is achieved between the output of main binary counter 314 and theoutput of character shift register 308. Comparison circuit 317 thereuponreturns a pulse on MATCH lead 266. State logic 301 then pulses INSERTlead 299, whereby a bit is inserted, in the first stage of shiftregister 315. Since shift register 315 has advanced to a position wherethe first stage corresponds to the addressee station, a bit is thusinserted in this stage to indicate that the station is designated as anaddressee station. Counter 314 and shift register 315 continue toadvance and the bit in the first stage is recycled through re-entrantgate 320 to the nth stage of register 315.

When main binary counter 314 advances to its maximum cycle count, n+1detector 327 is pulsed. This resets main binary counter 314 and pulsesstate logic 301 15 by way of n+1 lead 408. State logic 301 now removesthe energizing condition applied to ENABLE lead 267, stopping high speedclock 323 which, in turn, stops counter 314 and register 315 in theirinitial positions. The line controller now awaits the reception of thenext call-in code, whereupon the process is repeated.

If, during the heading reception state, the party line sending stationshould be interrupted, time out circuit 310 times out and pulses statelogic 301. State logic 301 thereupon goes to the major alarm statewherein the code sequence ENQ-EOT is generated and transmitted, clearingand restoring the party line station. Thereafter, a diagnostic printoutof the character sequence T-SPC is provided and a new test poll isinitiated in the same manner as previously described.

If, during the heading reception state, the sending station respondswith an improper code which is neither 2. Delete character, a call-in(CEC) character nor a start-of-text (STX) character, this is detected bycharacter detection gate 312 which, in turn, pulses state logic 301,indicating an improper code. In the event, state logic 301 similarlyadvances to the major alarm state, sending the code sequence ENQ-EOT,providing the diagnostic printout of the characters H-SPC wherein thecharacter H indicates a bad heading character. State logic 301 thenproceeds to the test poll state in the same manner as previouslydescribed.

Return now to the reception of the message heading during the headingreception state. The heading is terminated by the start-of-text ("STX)character. When this character is received, start-stop clock 309 resetstime out circuit 310 and shifts the character into register 308.Detection gates 312 then pulse state logic 301 to indicate the receptionof the code character STX. State logic 301 thereupon enters the headingdelivery state.

In the heading delivery state, state logic 301 energizes SPC lead 270,pulses WRITE lead 255 and START lead 251, and energizes EXTEND lead 256-in a manner to extend the output of register 308 to typing unit 304.Accordingly, as previously described, the station poll code of theoutlying station originating the message is passed to the typing unit.

At the end of the printout of the station poll code, start-stop clock309 pulses state logic 301. State logic 301 thereupon deletes the bit inthe first stage of main shift register 315. This enables high speedclock 323, which now concurrently advances counter 314 and register 315until the next bit appears in the first stage of the register. Thiscorresponds to the first addressee station designated by the addresscode in the heading of the message. At this time state logic 301arranges the generation and transmission of the code character ENQ,passing this character to the line and to typing unit 304. After thecharacter is generated, start-stop clock 309 again pulses state logic301, which, in turn, energizes CEC lead 337 to pass the call-in code toshift register 308 and then enables data control 305 to pass the call-incode to the output line and to typing unit 304. Accordingly, the codesequence ENQ-CEC (CEC designat ing the call-in code of the first addressstation), is transmitted to line 300 and printed by typing unit 304.State logic 301 also restarts time out circuit 310. The line controllernow awaits the response of the addressee station. The outlying stationsrecognize the code sequence as a selection sequence inquiring whetherthe station is prepared to receive a message. Finally, state logic 301restarts time out circuit 310.

The party line stations respond to the call-in code sequence with eitherthe code' character ACK, indicating that it is ready to receive, thecode character NAK, indicating that it is not ready to receive, or thecode character CAN, indicating that the prior message was receivedimproperly. In the event, however, that the addressee station respondswith an improper character, time out circuit 310 is reset and theimproper character is detected by character detection gates 312.

Gates 312, in turn, indicate to state logic 301 that an impropercharacter has been received. State logic 301 now energizes ENTER lead340 in a manner to insert a 1 bit in the final stage of main shiftregister 315. This has the effect, as will be seen hereinafter, ofrecirculating the bit corresponding to the addressee station from thefirst stage to the nth stage of register 315. State logic 301 also codeswrite gates 307 with the code character R and then arranges that thiscode character be sent to typing unit 304.

After the code character R is printed, state logic 301 energizes CEClead 337, whereby the call-in code of the addressee station is passed towrite gates 307. State logic 301 thereafter arranges that code characterCEC is printed by typing unit 304. Accordingly, if a bad response isreceived from the addressee station, state logic 301 arranges that thebad character response code character R with the addressee stationcall-in character be sent to typing unit 304. Thereafter, state logic301 deletes the bit in the first stage of main shift register 315,permitting the advance of register 315 and counter 314 to the nextaddressee station and thereupon sending the code sequence ENQ-CEC toinquire whether the next addressee station is ready to receive amessage. This sequence is, of course, sent to line 300 and to typingunit 304 to provide a printout indicating that the addressee station iscalled. Time out circuit 310 is restarted and the line controller nowawaits the response.

In the event that the addressee station fails to respond, time outcircuit 310 times out and pulses state logic 301. State logic 301thereupon arranges the generation of the code sequence T-CEC forapplication to typing unit 304 in substantially the same manner aspreviously described with respect to the failure of an addressee stationto respond with the proper character. In this event, of course, the codesequence comprises T-CEC, indicating that that addressee station failedto respond. State logic 301 also reinserts a bit in the final stage ofmain shift register 315 and then proceeds to delete the bit in the firststage of the register and send the code sequence ENQ-CEC of the nextaddressee station to line 300 and to the typing unit. Time out circuit310 is also restarted.

If the addressee station responds that the prior message was improperlyreceived by sending the code character CAN, time out circuit 310 isreset and character detection gate 312 indicates the reception of thischaracter to state logic 301. State logic 301 thereupon enters a bit inthe final stage of main shift register 315 and arranges the generationof the code sequence C-CEC for application to typing unit 304. Aprintout is thus provided to indicate that the addressee stationresponded that the prior message was improperly received. Thereafter,state logic 301 deletes the bit in the first stage of main shiftregister 315 and sends the code character sequence ENQ-CEC to line 300and to typing unit 304, thus inquiring whether the next addresseestation is ready to receive and at the same time providing a printout.State logic 301 also resets time out circuit 310 and the line controlleris prepared for the response of the addressee station.

If the addressee station responds that it cannot receive by returningthe code character NAK, start-stop clock 309 peset time out circuit 310and the character is inserted in register 308. Character detection gate312 pulses state logic 301, indicating that the character NAK has beenreceived. State logic 301, in turn, energizes ENTER leads 340 in amanner to insert a bit in the final stage of register 315. At this timestate logic 301 deletes the bit in the first stage of register 315 and,when the circuits advance to the next addressee station, arranges thegeneration of the code character sequence ENQ-CEC for application toline 300 and typing unit 304. Time out circuit 310 is again restartedand the line controller awaits the response of the next addresseestation.

If the addressee station responds that it is ready to receive byreturning the code character ACK, time out circuit 310 is reset andcharacter detection gate 312 indicates to state logic 301 that the codecharacter ACK" has been received. In this event state logic 301energizes ENTER leads 340 in a manner to insert a bit in the final stageof main shift register 315. This has the effect of clearing the nthstage and thus blocking the recirculation of the bit in the first stageto the nth stage of register 315. State logic 301 now deletes the bit inthe first stage of the register and generates the code charactersequence ENQ-CEC to inquire of the readiness of the next addresseestation. Time out circuit 310 is again restarted and the line controllerawaits the response of the addressee station.

To summarize the above described operations in the heading deliverystate, each addressee station is called when main shift register 315advances to the bit corresponding to the addressee station. This bit isrecirculated or entered in the final stage of register 315 if theaddressee station responds that it is not ready to receive, respondsthat the previous message was improperly received, responds with animproper character or fails to provide any response. Alternatively, thebit is discarded if the station responds that it is ready to receive.Main shift register 315 continues the advance to permit the calling ofeach addressee station, whereupon all bits corresponding to stationsresponding ACK are eliminated and all bits corresponding to stationshaving responses other than ACK are retained in main shift register 315.

When main shift register 315 is advanced through all of its stages, mainbinary counter 314 is, of course, concurrently advanced through all ofits corresponding positions. Upon main binary counter 314 being advancedto the last, or n-l- 1, position, n+1 detector 327 is operated to resetmain binary counter 314. Since main shift register 315 also has n+1stages, it is at this time completely recirculated and back to itsinitial position. Thus, with main shift register 315 back in its initialposition, n+1 detector 327 resets main binary counter 314 and all-0detector 326 pulses state logic 301 by way of ALL-0 lead 333. This pulseis passed to a counting arrangement in state logic 301 which maintainsthe count of the number of cycles of main binary counter 314.

The heading delivery process described above is now repeated with theexception that the addressee stations responding that they are ready toreceive are, of course, not called again since their corresponding bitshave been deleted from main shift register 315. At the completion ofthis second cycle, counter 314 is again reset, and a pulse is againapplied to state logic 301, which now indicates that two cycles havebeen completed. Subsequent cycles are similarly provided until eightcycles are completed. At this time state logic 301 advances to thealternate delivery state in the event that all of the addressee stationshave not responded that they are ready to receive. Alternatively, statelogic 301 advances to the end delivery state if all the addresseestations responded that they are prepared to receive.

Assume first that at least one station has not responded that it isprepared to receive. This fact is memorized by state logic 301 duringeach cycle and after the eighth cycle of counter 314 the subsequentpulse from high speed clock 323 applied by way of high speed CLOCK lead343 pulses state logic 301 which steps to the alternate delivery state.It is, of course, recalled that after sending the last CEC code andreceiving a response from the addressee station, the generation andtransmission of the code character sequence ENQCEC for the next stationis initiated. At this time, with state logic 301 advanced to thealternate delivery state, INSERT II lead 349 is pulsed, whereby a bit isinserted in the second stage of main shift register 315. Accordingly,register 315 and main binary counter 314 advance, as previouslydescribed, until the bit inserted in the second stage advances to thefirst stage. Accordingly, after the generation and transmission of thecode character ENQ, when CEC lead 337 is pulsed, the call-in code of thefirst addressee station corresponding to the second stage is generatedand transmitted to the line. This station is designated as thealternate, or intercept, station and will print a message headingconsisting of the call-in characters of the addressee stations who havenot responded that they are ready to receive.

It is noted that in the event the alternate delivery station returns abad response, or returns the code character NAK or CAN, or fails torespond, state logic 301 provides the usual operations (such as adiagnostic printout for a bad response, time out, etc.). DELETE lead 264is not pulsed, however, whereby the code sequence for calling thealternate delivery station is again repeated until this station respondswith the code character ACK. It is, of course, apparent that thealternate delivery station may be attended to insure that all alternatedelivery messages will be received. In addition, it is noted that thealternate delivery station preferably is arranged to print any incomingdata following the reception of its own call-in character.

After the alternate delivery station responds with the character ACK,detection gates 312 advise state logic 301 that this character has beenreceived. State logic 301 now proceeds to code write gates 307 with thecode character Delete and arranges the line controller to send the codecharacter to line 300. After the generation of this character start-stopclock 309 pulses state logic 301 which, in turn, repeats the sequencefor generating and transmitting the code character Delete. This cycle isrepeated six times, the six Delete characters being sent to thealternate delivery station to provide a leader in the tape which isconventionally punched at the alternate delivery station.

After the generation of the sixth Delete character, start-stop clock 309again pulses state logic 301 which, in turn, codes write gates 307 withthe code character SOH. This character is sent to line 300 and isrecorded by the alternate delivery station to indicate the start of themessage heading.

At the termination of the generation of the character SOH, start-stopclock 309 again pulses state logic 301. State logic 301 pulses DELETElead 264, advancing main shift register 315 and main binary counter 314to the next bit in register 315. This will correspond to the firstaddressee station which did not respond that it was ready to receive.State logic 301 also pulses CEC lead 337, thereby coding Write gate 307with the call-in character of this addressee station. The call-incharacter is thus sent to line 300, under the control of state logic301, to be recorded at the alternate delivery station.

After the generation and transmission of the call-in character, statelogic 301, in response to the pulse from start-stop clock 309, againdeletes the bit in the first stage of main shift register 315.Accordingly, register 315 and counter 314 advance to the next addresseestation which failed to respond that it was ready. At this time thecall-in character of this next station is transmitted to line 300 in thesame manner as previously described. This cycle is repeated until allthe addressee stations are called and all of the bits are deleted inmain shift register 315. Thus, the alternate delivery station hasrecorded in the message heading the call-in characters of each addresseestation which failed to respond that it was ready to receive.

When the final bit is deleted in main shift register 315, the register,together with counter 314, advance to their final positions. At thefinal position, n+1 detector 327 resets counter 31 4. Accordingly, apulse is applied to ALL-0 lead 333. This advances state logic 301 to theend delivery state.

With state logic 301 stepped to the end delivery state, INSERT lead 299is pulsed. This inserts a bit in the first stage of register 315 wherebyhigh speed clock 323 stops, maintaining register 315 and main binarycounter 314 in their initial positions. At this time, state logic 301codes the character *ENQ on write gates 307 and arranges thetransmission of the code to line 300. After the generation of this code,state logic 301 codes the device control character DC on write gates307, passing this code to line 300. As described hereinafter, the codecharacter sequence ENQ-DC is detected by all of the outlying stations,enabling the addressee stations who responded that they are ready tounblind and print all of the subsequent data text. After the codecharacter DC is transmitted, startstop clock 300 again pulses statelogic 301, which advances to the text state.

If all of the addressee stations had responded that they are ready toreceive the message, state logic 301 does not go into the alternatedelivery state. In this event state logic 301 does not record a negativeresponse from any addressee station while the line controller circuitsad- Vance through the eighth cycle. It is noted that all addresseestations may have responded ready prior to the eighth cycle, whereby thecircuits rapidly advance through the cycle without stopping. After theeighth cycle, therefore, and in response to the clock pulse on highspeed CLOCK lead 343, state logic 301 advances directly to the enddelivery state. In this state, as previously described, a bit isinserted in the first stage of register 31'5 whereby the register andcounter 314 are stopped in their initial positions. Thus, after thegeneration of the code character ENQ and in response to the pulse fromstartstop clock 309, state logic 301 codes device control character DCon Write gates 307 and arranges for the character to be passed to line300 in the same manner as previously described. State logic 301 thenadvances to the text state after the transmission of the code characterDC.,9

With state logic 301 stepped to the text state, the startof-textcharacter STX is coded on write gate 307. State logic 301 then arrangesto pass the code character to line 300. When the start-of-text characterSTX is received by the outlying station selected to send the datamessage, this station will proceed to send the message text, asdescribed hereinafter. At the same time, state logic 301 restarts timeout circuit 310. Accordingly, the originating station sends the messagetext to all the addressee stations Who are prepared to receive and tothe alternate delivery stations if one or more of the addressee stationsindicated it was not prepared to receive.

During the transmission of the message text, each incoming characterstarts up start-stop clock 309. Startstop clock 309' resets time outcircuit 310 and thereafter pulses state logic 301 which, in turn,restarts time out circuit 310. Accordingly, the text is monitored by theline controller which checks to see if there is a message interruption.

Assume now that the message is interrupted. This permits time outcircuit 310 to time out, pulsing T/O lead 274. State logic 301 thereupongoes to the major alarm state. In this state, as previously described,the code character sequence ENQ-EOT is generated and transmitted to stopand clear all of the outlying stations, including the sending station,the addressee stations and the alternate delivery station. In addition,a diagnostic printout is provided. This printout includes the codecharacter sequence T-SPC (the SPC character being derived from the lastpoll store binary counter 316 identifying the sending station).Thereafter, as previously described, the line controller returns to thetest poll state, a new test polling is started and, when a properresponse is received, a new poll is initiated.

Under normal conditions the message text is terminated by theend-of-text code character EOT. When this character is received by dataset 302 and insert d y startstop clock 309 into character shift register308, character detection gate 312 signals state logic 301, whichadvances, to the idle line state.

In the idle line condition, state logic 301 energizes INHIBIT lead 401.Data control 305 proceeds to block signals from the receive portion ofdata set, thereby blinding shift register 308 and start-stop clock 309to incomingsignals. At the same time, state logic 301 codes write gates307 with the code character DIJE, passing this code character to line300. At this time the transmitting station may continue to send Deletecharacters. Since the line controller is blinded, these characters willbe discarded. It is noted at this time that the transmission of the codecharacter DLE places the outlying stations in the poll state, preparedto receive their poll characters since the character DLE does notimmediately follow the major alarm ENQ-EOT code sequence, which codesequence would place the outlying stations in the text poll state.Accordingly, the outlying stations recognize that the line controller isabout to go into the poll state.

In the idle line state, state logic 301 provides no further functionuntil incoming line 300' goes idle. At this time idle line timer 403,which timer is connected to the output of the receive side of data set302, begins to time out. If incoming line 300 is idle for apredetermined length of time, idle line timer 403 passes a pulse by wayof IDLE lead 392 to state logic 301. This advances state logic 301 backto the poll state wherein, as previously described, the skip table ispassed to main shift register 315. Register 315, with counter 314, willadvance until a match is obtained with last poll store binary counter316. The bit is now deleted from the first stage of main shift register315 to advance the circuits to the next outlying station to be polled.

After all of the outlying stations are polled counters 314 and 316advance to their final positions and register 315 recycles to itsinitial position. At this final position, counters 314 and 316 arereset, as previously described. When main binary counter 314 is reset,all-0 detector 326 pulses state logic 301. Thereupon, upon theapplication of the next clock pulse to high speed clock 343, state logic301 again inserts the skip table into main shift register 315 anddeletes the bit in the first stage of the register. Accordingly, thecircuits again advance to the first station to be polled.

PARTY LINE STATIONS Refer now to FIG. 2 which discloses a party linestation suitable for cooperating with the main station line controller.The system contemplates a plurality of party line stations, each ofwhich is substantially identical to the station shown in FIG. 2. Eachstation preferably includes a data set, such as data set 500, whichoperates in substantially the same manner as the data set in the linecontroller. Accordingly, incoming line signals from line 300 areconverted into data signals by the receive portion of data set 500 andthese data signals are applied to input selector 502. Alternatively,output data signals applied by output selector 503 to the send portionof data set 500 are converted to line signals for application to line300.

Each outlying station is provided with a terminal attendant set,generally indicated by block 501. The terminal attendant set preferablyincludes a transmitter, such as a message tape transmitter, and arecorder or a data printer. Terminal attendant set 501 also includes theconventional keys and lamps and simple logic circuits necessary forproviding supervisory functions, described hereinafter.

Terminal attendant set 501 is arranged to start the tape transmittertherein when incoming terminal lead START is energized. The tapetransmitter thereupon applies serial data to terminal OUT which extendsto an input of input selector 502. The recorder in terminal attendantset 501 is unblinded when incoming terminal lead PRINT is energized,whereby incoming serial data applied to termi-t

